c o p y r igh t @ w i n s em i microelectronics c o . , lt d . , a l l ri g h t r e s er v ed . w w w w cd8c60s cd8c60s cd8c60s cd8c60s rev.a oct .2010 sensitive sensitive sensitive sensitive gate gate gate gate silicon silicon silicon silicon controlled controlled controlled controlled rectifiers rectifiers rectifiers rectifiers features ? sensitive gate trigger current:i gt =200 a maximum ? low on-state voltage :v tm =1.2(typ.) @ i tm ) ? low reverse and forward blocking current: i drm /i r rm =1ma@tc=125 ? low holding current :i h =5ma maximum general description sensitive gate triggering scr is suitable for the application where gate current limited such as microcontrollers, logic integrated circuits,small motor control, gate driver for large scr,sensing and detecting circuits.general purpose switching and phase control applications absolute maximum ratings ( t j = 25 c unless otherwise specified ) symbol parameter value units v drm /v rrm repetitive peak off-state voltage (note(1) 600 v i t(av) average on-state current ( 180 conduction angle ) t i = 110 c 5 a i t(rms) r.m.s on-state current ( 180 conduction angle ) t i = 110 c 8 a i tsm non repetitive surge peak on-state current tp=8.3ms 73 a tp=10ms 70 i 2 t i 2 t value for fusing t p = 10 ms 24.5 a 2 s di/dt critical rate of rise of on-state current i tm =2a;ig=10ma; di g /dt=100a/ s t j =125 c 50 a/ ? p g(av) average gate power dissipation t j =125 c 1 w i fgm peak gate current t j =125 c 4 a v rgm reverse peak gate voltage t j =125 c 5 v t j junction temperature -40~125 c t stg storage temperature -40~150 c note1:although not recommended,off-state voltages up to 800v may be applied without damage,but the thyristor may switch to the on-stage.the rate of rise of current should not exceed15a/ s. thermal characteristics symbol parameter value units min typ max r j c thermal resistance junction to case - - 20 /w r j a thermal resistance junction to ambient - - 70 /w
steady, steady, steady, steady, keep keep keep keep you you you you advance advance advance advance w w w w cd8c60s cd8c60s cd8c60s cd8c60s 2 / 5 electrical characteristics (t j =25 ,r gk =1k ? unless otherwise specified ) symbol characteristics value units min typ max i drm /i rrm off-state leakage current (v ak =v drm /v rrm ) t c =25 - - 5 a t c =125 1 m a v tm forward "on"voltage (i tm =16a tp=380 s) (note2.1) - 1.2 1. 6 v i gt gate trigger current (continuous dc) (v ak =12vdc,r l =140 ? ) (note2.2) - - 200 a v gt gate trigger voltage (continuous dc) (v ak =12vdc,r l =140 ? ) (note2.2) - - 0.8 v v gd gate threshold voltage (v d =12v drm rl=3.3k ? r gk =220 ? ) (note2.1) 0. 1 - - v dv/dt critical rate of rise off-state voltage (v d =0.67v drm ; r gk =220 ? ) t j =125 5 - - v/ ? i h holding current (v d =12v;i gt =0.5ma) - 2 5 ma i l latching current (v d =12v;i gt =0.5ma) - 2 6 ma rd dynamic resistance t j =125 - - 46 m ? *notes: *notes: *notes: *notes: 2.1 pulse width 1.0ms,duty cycle 1% 2.2 r gk current is not included in measurement.
steady, steady, steady, steady, keep keep keep keep you you you you advance advance advance advance w w w w cd8c60s cd8c60s cd8c60s cd8c60s 3 / 5 0 0 0 0 fig. fig. fig. fig. 3 3 3 3 surge peak on-state current versus number of cycles. fig. fig. fig. fig. 4 4 4 4 on-state characteristics (maximum values) fig.5 fig.5 fig.5 fig.5 non-repetitive surge peak on-state current for a sinusoidal pulse with width tp < 10ms and corresponding value of l 2 t fig.6 fig.6 fig.6 fig.6 relative variation of gate trigger current and holding versus junction temperature fig.1 fig.1 fig.1 fig.1 maximum average power dissipation versus average on-state current fig fig fig fig .2 .2 .2 .2 average and d.c.on-state current versus ambient temperature (device mounted on fr4 with recommended pad layont
steady, steady, steady, steady, keep keep keep keep you you you you advance advance advance advance w w w w cd8c60s cd8c60s cd8c60s cd8c60s 4 / 5 fig.8 fig.8 fig.8 fig.8 relative variation of dv/dt immunity versus gate-cathode capacitance (typical values) fig. fig. fig. fig. 7 7 7 7 relative variation of dv/dt immunity versus gate-cathode resistance (typical values) fig.8 fig.8 fig.8 fig.8 thermal resistance junction to ambient versus copper surface under tab (epoxy printedcircuit board fr4,copper thickness:35 m)
steady, steady, steady, steady, keep keep keep keep you you you you advance advance advance advance w w w w cd8c60s cd8c60s cd8c60s cd8c60s 5 / 5 to to to to -252 -252 -252 -252 package package package package dimension dimension dimension dimension unit: mm
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